TFT-LCD驱动器的液晶显示模块(LCD module)及SIDP接收特性

 
Figure 5. The waveform of an input signal of transmitter and output signal of receiver.
图5发射机和接收机的输出信号的输入信号的波形图
Fig. 5 shows the waveform of signals at the output node of the pattern generator (input signal of transmitter) and the input node of the LCD module (output signal of receiver) at the pixel clock frequency of 20MHz, which means that serialized data rate is 300Mbps/ch. The signal at the top, a RGB signal, is applied to the transmitter chip and the signal at the bottom is recovered from the receiver with a propagation delay of 264ns which is gate delay in the transmitter and receiver.
图5示出了在图案产生器（发射器）的输入信号的输出节点的信号的波形的LCD模块（接收器）输出信号的输入节点，在像素时钟频率为20MHz，表示序列化的数据速率是300Mbps的/ ch的。在顶部，一个RGB信号#p#分页标题#e#，该信号被施加到发射器芯片，并回收在底部的信号从接收器的传播延迟是在发射器和接收器的门延迟264ns。

Figure 6. The image of the LCD module
图6 液晶显示模块的形象
Fig. 6 shows the image of LCD module at the data rate of 300Mbps/ch. In the module test, the data transfer rate was tested up to 337Mbps/ch which is the maximum frequency for VGA application. In addition, the driver IC is also tested on wafer level and the maximum data rate of the receiver has been measured at 400Mbps/ch.
图6示出在数据速率300Mbps/ch的图像液晶显示模块。模块的测试，测试的数据传输速率高达337Mbps/ch（VGA）系统的最大频率。此外，在驱动器IC上测试晶圆级和最大数据传输速率#p#分页标题#e#的接收器以400Mbps/ch测量的。
Table 1 summarizes the measured performance characteristics of the SiDP receiver. The minimum input differential voltage is 70mV and the common mode voltage range is from 0.6V to 1.2V. The number of data channel can be selected in 1 or 2 according to the display resolution and color depth. In case of two data channel mode, the current consumption is 5.4mA at the data rate of 300Mbps/ch. This data rate can support up to 24-bit VGA display. The input load termination resistor of 80~120Ÿ is internally implemented on a chip.
表1总结了SIDP接收器测得的性能特点。最小的输入差分电压为70mV的共模电压范围是从0.6V到1.2V。可以选择在1或2的数据信道的数量，根据显示器的分辨率和颜色深度。在两个数据信道模式的情况下，电流消耗在数据速率300Mbps/ch#p#分页标题#e#的5.4毫安。此数据速率最多可支持24位VGA显示器。输入负载端接电阻为80〜120Y内部实现在一个芯片上。

Table 1. Characteristics for SiDP receiver
表1 SIDP接收特性
5. Conclusions
总结
The SiDP receiver is realized in a 0.18um high voltage CMOS technology for a mobile 24-bit hVGA TFT-LCD driver IC. The receiver adopts SubLVDS as a physical layer and supports 1 and 2 data channels depending on the bandwidth needed. The number of signal lines going through the hinge of a mobile phone is reduced from 28 down to 6. The maximum transfer rate is up to 800Mbps for two data channel. The current consumption is 5.4mA at the data rate of 600Mbps.
SIDP接收机在0.18微米高压CMOS技术，通过移动24位HVGA TFT-LCD驱动IC来实现。接收机采用SubLVDS作为物理层，并支持1#p#分页标题#e#和2的数据信道，根据所需要的带宽。信号线的数目的移动电话的铰链经历从28减少到6。最大传输速率高达800Mbps的两个数据通道。该电流消耗5.4毫安的600Mbps的数据速率。
6. Acknowledgements
致谢
The authors would like to thank Texas Instruments for the transmitter http://ukthesis.org/ygsslwdx/ chips and PCBs.
笔者感谢德州仪器发射机芯片和多氯联苯。
7. References
参考资料
[1] Qualcomm, “Mobile Display Digital Interface Specification”, 2003.
[2] MIPI, “Draft MIPI alliance D-PHY specification”, 2005.
[3] Nokia, “Compact Display Specification”, 2005.